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Micrel, Inc.
3.3V, 3.2Gbps DIFFERENTIAL 4:1 LVDS MULTIPLEXER with 1:2 FANOUT and INTERNAL TERMINATION
Precision Edge SY89547L
Precision Edge(R) SY89547L (R)
FEATURES
Selects among four differential inputs Provides two copies of the selected input Guaranteed AC performance over temp and voltage: * DC-to > 3.2Gbps data rate throughput * < 620ps In-to-Out tpd * < 150ps tr/tf Unique input isolation design minimizes crosstalk Ultra-low jitter design: * < 1psRMS random jitter * < 10psPP deterministic jitter * < 10psPP total jitter (clock) * < 0.7psRMS crosstalk-induced jitter Internal input termination Unique input termination and VT pin accepts DCcoupled and AC-coupled inputs (LVDS, LVPECL, CML) 350mV LVDS output swing Power supply 3.3V 10% -40C to +85C temperature range Available in 32-pin (5mm x 5mm) MLFTM package Precision Edge(R)
DESCRIPTION
The SY89547L is a precision, high-speed 4:1 differential multiplexer that provides two copies of the selected input. The high speed LVDS (350mV) compatible outputs with a guaranteed throughput of up to 3.2Gbps over temperature and voltage. The SY89547L differential inputs include Micrel's unique, 3-pin internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards, both AC- and DC-coupled without external resistor-bias and termination networks. The result is a clean, stub-free, low jitter interface solution. The SY89547L operates from a single 3.3V supply, and is guaranteed over the full industrial temperature range (-40C to +85C). For applications that require a 2.5V supply, consider the SY89546U. For applications that only require one differential output, consider the SY89544U or SY89545L. The SY89547L is part of a Micrel's Precision Edge(R) product family. All support documentation can be found on Micrel's web site at: www.micrel.com.
APPLICATIONS
SONET/SDH multi-channel select applications Fibre Channel applications GigE applications
FUNCTIONAL BLOCK DIAGRAM
IN0 50 VT0 50 /IN0
4:1 MUX 1:2 Fanout
TYPICAL PERFORMANCE
Output Amplitude vs. Frequency
0 IN1 50 VT1 50 /IN1 1 MUX IN2 50 VT2 50 /IN2 3 S0 2
Q0 /Q0
LVDS
400 OUTPUT AMPLITUDE (mV) 350 300 250 200 150 100 50 0 0
Q1 /Q1
S1
IN3
1000 2000 3000 4000 5000 6000 FREQUENCY (MHz)
50 VT3 50 /IN3 SEL0 (CMOS/TTL)
Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology. M9999-060906 hbwhelp@micrel.com or (408) 955-1690
SEL1 (CMOS/TTL)
Rev.: B Amendment: /1
1
Issue Date: June 2006
Micrel, Inc.
Precision Edge(R) SY89547L
PACKAGE/ORDERING INFORMATION
IN1 VT1 /IN1 VCC VCC IN2 VT2 /IN2
Ordering Information(1)
VCC IN3 VT3 /IN3 VCC SEL1 GND VCC
32 31 30 29 28 27 26 25
VCC /IN0 VT0 IN0 VCC SEL0 GND VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
24 23 22 21 20 19 18 17
Part Number SY89547LMI SY89547LMITR(2) SY89547LMG(3) SY89547LMGTR(2, 3)
Package Type MLF-32 MLF-32 MLF-32 MLF-32
Operating Range Industrial Industrial Industrial Industrial
Package Marking SY89547L SY89547L SY89547L with Pb-Free bar-line indicator SY89547L with Pb-Free bar-line indicator
Lead Finish Sn-Pb Sn-Pb Pb-Free NiPdAu Pb-Free NiPdAu
32-Pin MLF(R)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC electricals only. 2. Tape and Reel. 3. Recommended for new designs.
PIN DESCRIPTION
Pin Number 4, 2, 32, 30, 27, 25, 23, 21 Pin Name IN0, /IN0, IN1, /IN1, IN2, /IN2, IN3, /IN3 Pin Function Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50. Note that these inputs will default to an indeterminate state if left open. Unused differential input pairs can be terminated by connecting one input to VCC and the complementary input to GND through a 1k resistor. The VT pin is to be left open in this configuration. Please refer to the "Input Interface Applications" section for more details. Input Termination Center-Tap: Each side of the differential input pair, terminates to a VT pin. The VTA0, VTA1, VTB0, VTB1 pins provide a center-tap to a termination network for maximum interface flexibility. See "Input Interface Applications" section for more details. These single-ended TTL/CMOS compatible inputs select the inputs to the multiplexers. Note that these inputs are internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. Input switching threshold is VCC/2. Positive Power Supply: Bypass with 0.1F0.01F low ESR capacitors. Differential Outputs: These LVDS output pairs are the outputs of the device. They are a logic function of the INA0, INA1, INB0, INB1 and SELA and SELB inputs. Please refer to the "Truth Table'" for details. If an output is not used, it must be terminated with 100 across the differential pair. Ground: Ground pin and exposed pad must be connected to the same ground plane.
3, 31, 26, 22
6, 19
1, 5, 8, 17, 20, 24, 28, 29 10, 11, 14, 15
7, 9, 12, 13, 16, 18
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GND Q /Q GND GND Q1 /Q1 GND
VT0, VT1, VT2, VT3 SEL0, SEL1
VCC Q0, /Q0, Q1, /Q1
GND, Exposed pad
2
Micrel, Inc.
Precision Edge(R) SY89547L
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ............................... - 0.5V to + 4.0V Input Voltage (VIN) ........................................ -0.5V to VCC Termination Current(3) Source or sink current on VT ..................................... 100mA Input Current Source or sink current on IN, /IN .......................... 50mA Lead Temperature (soldering, 20 sec.) ................... +260C Storage Temperature (TS) ...................... -65C to +150C
Operating Ratings(2)
Supply Voltage (VCC) ..................................... 3.0V to 3.6V Ambient Temperature (TA) ........................ -40C to +85C Package Thermal Resistance(4) MLF(R) (JA) Still-Air ................................................................ 35C/W 500lfpm .............................................................. 28C/W MLF(R) (JB) Junction-to-Board ............................................... 20C/W
DC ELECTRICAL CHARACTERISTICS(5)
TA = -40C to +85C; Unless otherwise stated. Symbol VCC ICC RDIFF_IN RIN VIH VIL VIN VDIFF_IN IN-to-VT
Notes: 1. Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to "Absolute Maximum Ratings" conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Due to the limited drive capability use for input of the same package only. 4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential (GND) on the PCB. JB uses 4-layer JA in still-air unless otherwise stated. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. Includes current through internal 50 pull-ups. 7. VIH(min) not lower than 1.2V. 8. See "Operating Characteristics" section for VIN and VDIFF_IN definition.
Parameter Power Supply Power Supply Current Differential Input Resistance (IN-to-/IN) Input Resistance (IN-to-VT, /IN-to-VT) Input High Voltage (IN, /IN) Input Low Voltage (IN, /IN) Input Voltage Swing (IN, /IN) Differential Input Voltage Swing | IN - /IN |
Condition
Min 3.0
Typ 3.3 68
Max 3.6 90 120 60 VCC VIH-0.1 VCC 2 x VCC 1.8
Units V mA V V mV mV V
No Load, Max. VCC
(6)
80 40 Note 7 Note 7 Note 7, 8 Note 7, 8 Note 8 VCC-1.6 0 100 200
100 50
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Micrel, Inc.
Precision Edge(R) SY89547L
LVDS OUTPUTS DC ELECTRICAL CHARACTERISTICS(9)
VCC = 3.3V 10%; TA = -40C to +85C; RL = 100 across Q and /Q, unless otherwise stated. Symbol VOH VOL VOUT VDIFF-OUT VOCM VOCM Parameter Output HIGH Voltage (Q, /Q) Output LOW Voltage (Q, /Q) Output Voltage Swing (Q, /Q) Differential Output Voltage Swing | Q - /Q| Output Common Mode Voltage (Q, /Q) Change in Common Mode Voltage (Q, /Q) Condition See Figure 5a See Figure 5a See Figures 1a, 5a See Figure 1b See Figure 5b See Figure 5b 0.925 250 500 1.125 -50 350 700 1.275 +50 Min Typ Max 1.475 Units V V mV mV V mV
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS(9)
VCC = 3.3V 10%; TA = -40C to +85C; unless otherwise stated. Symbol VIH VIL IIH IIL
Note: 9. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current
Condition
Min 2.0
Typ
Max VCC 0.8 40 -300
Units V V A A
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Micrel, Inc.
Precision Edge(R) SY89547L
AC ELECTRICAL CHARACTERISTICS(10)
VCC = 3.3V 10%; TA = -40C to +85C; RL = 100 across Q and /Q, unless otherwise stated. Symbol fMAX tpd tSKEW Parameter Maximum Operating Frequency VOUT 200mV Differential Propagation Delay IN-to-Q SEL-to-Q Input-to-Input Skew Output-to-Output Skew Part-to-Part Skew tJITTER Data Random Jitter (RJ) Deterministic Jitter (DJ) Clock Total Jitter (TJ) Cycle-to-Cycle Jitter Crosstalk tR, tF
Notes: 10. Measured with 100mV input swing. See "Timing Diagrams" section for definition of parameters. High frequency AC parameters are guaranteed by design and characterization. 11. Input-to-input skew is the difference in time from an input-to-output in comparison to any other input-to-output. In addition, the input-to-input skew does not include the output skew. 12. Output-to-output skew is measured between two different outputs under identical input transitions. 13. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. Total skew is calculated as the RMS (Root Mean Square) of the input skew and output skew. 14. RJ is measured with a K28.7 comma detect character pattern, measured at 1.25Gbps and 3.2Gbps. 15. DJ is measured at 1.25Gbps and 3.2Gbps, with both K28.5 and 223-1 PRBS pattern. 16. Total jitter definition: with an ideal clock input of frequency fMAX, no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value. 17. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn-Tn-1 where T is the time between rising edges of the output signal. 18. Crosstalk is measured at the output while applying two similar clock frequencies to adjacent inputs that are asynchronous with respect to each other at the inputs.
Condition NRZ Data Clock
Min 3.2
Typ
Max
Units Gbps
4 340 200 440 420 5 8 540 700 20 20 200 1 10 10 1 0.7 40 80 150
GHz ps ps ps ps ps psRMS psPP psPP psRMS psRMS ps
Note 11 Note 12 Note 13 Note 14 Note 15 Note 16 Note 17 Note 18 At full output swing
Crosstalk-Induced Jitter Output Rise / Fall Time (20% to 80%)
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Micrel, Inc.
Precision Edge(R) SY89547L
SINGLE-ENDED AND DIFFERENTIAL SWINGS
VIN, VOUT 350mV (Typ.)
VDIFF_IN, VDIFF_OUT 700mV (Typ.)
Figure 1a. Single-Ended Voltage Swing
Figure 1b. Differential Voltage Swing
TIMING DIAGRAM
IN /IN tpd Q /Q
SEL SEL-to-Q tpd Q /Q
Figure 2. Timing Diagram
TRUTH TABLE
IN0 0 1 X X X X X X IN1 X X 0 1 X X X X IN2 X X X X 0 1 X X IN3 X X X X X X 0 1 SEL0 0 0 1 1 0 0 1 1 SEL1 0 0 0 0 1 1 1 1 Q 0 1 0 1 0 1 0 1 /Q 1 0 1 0 1 0 1 0
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Micrel, Inc.
Precision Edge(R) SY89547L
FUNCTIONAL CHARACTERISTICS
VCC = 3.3V, GND = 0V, VIN = 100mV, TA = 25C.
200MHz Output
1.6GHz Output
Output Swing (100mV/div.)
Output Swing (100mV/div.)
Q
Q
/Q /Q
TIME (600ps/div.)
TIME (80ps/div.)
2.5GHz Output
3.2GHz Output
Output Swing (100mV/div.)
Output Swing (100mV/div.)
Q
Q
/Q
/Q
TIME (50ps/div.)
TIME (40ps/div.)
622Mbps Mask (2
23
1 PRBS)
2.5Gbps Mask (2
23
1 PRBS)
Output Swing
Output Swing
(100mV/div.)
(100mV/div.)
TIME (400ps/div.)
TIME (100ps/div.)
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Micrel, Inc.
Precision Edge(R) SY89547L
FUNCTIONAL CHARACTERISTICS
VCC = 3.3V, GND = 0V, VIN = 100mV, TA = 25C.
3.2Gbps Data Output (223-1 PRBS)
Output Swing (100mV/div.)
TIME (80ps/div.)
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Micrel, Inc.
Precision Edge(R) SY89547L
INPUT AND OUTPUT STAGE INTERNAL TERMINATION
VCC
IN 50 VT 50 /IN GND
Figure 3. Simplified Differential Input Stage
INPUT INTERFACE APPLICATIONS
VCC
VCC
VCC
IN
IN
IN CML /IN SY89547L GND NC VT
LVPECL
CML /IN SY89547L GND VCC -1.4V VT
GND
/IN VCC 0.01F VT Rp For VCC = 3.3V, Rp = 50 SY89547L
GND
Figure 4a. CML Interface (DC-Coupled)
Figure 4b. CML Interface (AC-Coupled)
Figure 4c. LVPECL Interface (DC-Coupled)
VCC
VCC
IN
LVPECL
IN
/IN Rp GND GND GND For VCC = 3.3V, Rp = 100 Rp VCC -1.4V VT SY89547L
LVDS /IN SY89547L GND NC VT
Figure 4d. LVPECL Interface (AC-Coupled)
Figure 4e. LVDS Interface
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Micrel, Inc.
Precision Edge(R) SY89547L
OUTPUT INTERFACE APPLICATIONS
LVDS specifies a small swing of 350mV typical, on a nominal 1.25V common mode above ground. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is kept to a minimum, to keep EMI low.
509
VOUT VOH, VOL 100
VOH, VOL
509 GND
,VOCM
VOCM,
GND
Figure 5a. LVDS Differential Measurement
Figure 5b. LVDS Common Mode Measurement
RELATED MICREL PRODUCTS AND SUPPORT DOCUMENTATION
Part Number SY89542U SY89543L SY89544U SY89545L SY89546U Function 2.5 V, 3.2Gbps Dual, Differential 2:1 LVDS Multiplexer with Internal Input Termination 3.3V, 3.2Gbps Dual, Differential 2:1 LVDS Multiplexer with Internal Input Termination 2.5V, 3.2Gbps, Differential 4:1 LVDS Multiplexer with Internal Input Termination 3.3V, 3.2Gbps 4:1 LVDS Multiplexer with Internal Input Termination 2.5V, 3.2Gbps, Differential 4:1 LVDS Multiplexer with 1:2 Fanout and Internal Termination MLFTM Application Note HBW Solutions New Products and Applications Data Sheet Link http://www.micrel.com/_PDF/HBW/sy89542u.pdf http://www.micrel.com/_PDF/HBW/sy89543l.pdf http://www.micrel.com/_PDF/HBW/sy89544u.pdf http://www.micrel.com/_PDF/HBW/sy89545l.pdf http://www.micrel.com/_PDF/HBW/SY89546u.pdf www.amkor.com/products/notes_papers/MLF_AppNote_0902.pdf www.micrel.com/product-info/products/solutions.shtml
M9999-060906 hbwhelp@micrel.com or (408) 955-1690
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Micrel, Inc.
Precision Edge(R) SY89547L
32-PIN MicroLeadFrame(R) (MLF-32)
Package EP- Exposed Pad
Die
CompSide Island
Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane
PCB Thermal Consideration for 32-Pin MLF(R) Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: 1. Package meets Level 2 qualification. 2. All parts are dry-packaged before shipment. 3. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated. M9999-060906 hbwhelp@micrel.com or (408) 955-1690
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